1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for manufacturing a cylindrical storage electrode of a semiconductor device.
2. Description of the Related Art
As semiconductor devices become more highly integrated, the pattern size becomes also smaller, resulting in a number of problems. Particularly, in highly-integrated semiconductor memory devices such as a dynamic random access memory (DRAM), the area occupied by a memory cell has been continuously reduced. Thus, it is necessary to improve memory cell characteristics to offset the reduced cell area. In DRAM devices, the memory cell characteristics depend on the capacitance of a cell capacitor constituting a memory cell. In other words, if the cell capacitance increases, the memory cell characteristics such as low-voltage characteristic and soft-error characteristics due to a particles can be improved. Since the cell capacitance is proportional to the surface area of a storage electrode of a capacitor, a highly efficient memory cell can be attained by increasing the surface area of the storage electrode. Therefore, in order to provide a storage electrode having an increased surface area within a limited area, three-dimensional storage electrodes, for example, a cylindrical storage electrode, have been proposed.
FIGS. 1 through 4 are cross-sectional views for illustrating a method for forming a conventional cylindrical storage electrode.
Referring to FIG. 1, an interlayer insulator film 120 is formed on a semiconductor substrate 100 having an active region 110 defined by isolation regions (not shown). Next, a predetermined photoresist layer pattern (not shown) is formed on the interlayer insulator film 120. Then the exposed portions of the interlayer insulator film 120 are etched using the photoresist layer pattern as an etching mask. Then, contact holes are formed to expose the active region 110 of the semiconductor substrate 100. Subsequently, a conductive layer 130 is formed to completely fill the contact holes.
Referring to FIG. 2, the resultant structure shown in FIG. 1 is planarized to form contact pads 130xe2x80x2 completely buried in the interlayer insulator film 120. Conventionally, the planarization is performed by an etch-back process using a dry etching process on the resultant structure until the surfaces of the interlayer insulator film 120 are exposed. Here, the upper surfaces of the contact pads 130xe2x80x2 formed according to the etch-back process are recessed because of an etching selectivity between the interlayer insulator film 120 such as a silicon oxide (SiO2) layer, and the conductive layer (130 of FIG. 1) such as a polysilicon layer. Subsequently, a silicon nitride (Si3N4) layer 140 used as an etching stop layer is formed on the surfaces of the interlayer insulator film 120 and contact pads 130xe2x80x2. As described above, since the upper surfaces of the contact pads 130xe2x80x2 are recessed, the silicon nitride layer 140 formed thereon is also recessed.
Next, referring to FIG. 3, an oxide layer 150 is formed on the silicon nitride layer 140. Then, a photoresist layer pattern (not shown) is formed on the oxide layer 150. Subsequently, the exposed portions of the oxide layer 150 are etched using the photoresist layer pattern as an etching mask. The etching stops at the silicon nitride layer 140 that is an etching stop layer. Then, openings which expose the surface of the silicon nitride layer 140 corresponding to the surfaces of the contact pads 130xe2x80x2 are formed in the oxide layer 150. Next, in order to expose the contact pads 130xe2x80x2, the exposed portions of the silicon nitride layer 140 are removed, conventionally by a dry etching process using plasma.
Referring to FIG. 4, since the drying etching process using plasma is isotropically performed, the surfaces of the contact pads 130xe2x80x2 are partially exposed. Thus, when the etching is completed, a silicon nitride layer 140xe2x80x2 partially remains in the form of spacers along the edges of the contact pads 130xe2x80x2, which is indicated by xe2x80x9cAxe2x80x9d in FIG. 4. The portions of the silicon nitride layer 140xe2x80x2 partially remain in the form of spacers and undesirably reduce the contact area between storage electrodes (not shown) and the contact pads 130xe2x80x2. In its worst case, the remaining portions of the silicon nitride layer 140xe2x80x2 may prevent a contact between storage electrodes (not shown) and the contact pads 130xe2x80x2, leading to device failure.
To solve the above problems, it is an objective of the present invention to provide a cylindrical storage electrode for a semiconductor device, which allows the storage electrode to contact a pad oxide layer by completely removing the exposed portion of a silicon nitride layer formed on the pad oxide layer as an etching stop layer in the course of manufacturing the cylindrical storage electrode.
Accordingly, to achieve the above objective, there is provided a method for manufacturing a cylindrical storage electrode of a semiconductor device including the steps of (a) forming a contact pad to be connected to an active region of a semiconductor substrate in an interlayer insulator film on the semiconductor substrate, (b) forming a silicon nitride layer as an etching stop layer on the contact pad, (c) forming an insulating layer on the silicon nitride layer, (d) exposing a portion of the surface of the silicon nitride layer by partially removing the insulating layer, (e) removing the exposed portion of the silicon nitride layer using a wet etching process using a predetermined etchant to expose the surface of the contact pad, (f) forming a conductive layer for a storage electrode on the insulating layer and the surface of the exposed contact pad, and (g) completing a cylindrical storage electrode by removing the upper portion of the conductive layer for a storage electrode, the insulating layer and the silicon nitride layer.
The contact pad may be formed of polysilicon.
Preferably, the silicon nitride layer is formed to a thickness of 100 to 500 xc3x85.
In the step (e), the etchant is preferably a phosphoric acid solution and the wet etching process is preferably performed at a temperature of 100 to 170xc2x0 C. for 4 to 30 minutes.
The conductive layer for a storage electrode may be formed of polysilicon.
The step (f) is preferably performed by deposition.
The step (g) may include the sub-steps of forming a flowable oxide layer on the conductive layer for a storage electrode, partially removing the insulating layer, the conductive layer for a storage electrode and the flowable oxide layer by performing an etch-back process on the entire surface of the resultant structure to expose the insulating layer, and sequentially removing the insulating layer and the silicon nitride layer.
Here, the flowable oxide layer is preferably either an undoped silicate glass (USG) layer or a boron phosphorus silicate glass (BPSG) layer, and the flowable oxide layer is preferably formed by a chemical vapor deposition (CVD) method.
According to the method of the present invention, in order to remove an etching stop layer, e.g., silicon nitride layer, formed on the contact pad, a wet-etching process using a phosphoric acid solution is used. Thus, the silicon nitride layer on the contact pad can be completely removed. Accordingly, the contact area between the contact pad and the storage electrode formed thereon can be maximized.